Managed Language Runtimes on Heterogeneous Hardware: Optimizations for Performance, Efficiency and Lifetime ImprovementPASS invited talk
Modern hardware is increasingly becoming heterogeneous to help improve the efficiency of our software and systems. Processors incorporating cores with diverse performance and power characteristics are already found in mobile devices. Software running on such processors can choose between a high performing but power hungry core or a slow core with lower power consumption. Individual cores can further be clocked at different frequencies. This shift towards heterogeneity is not limited to processors alone. The challenge to scale DRAM beyond 20 nm led scientists to look for new memory technologies. Of the known alternatives, phase change memory is the most promising. But owing to certain drawbacks, of which higher latency and limited lifetime are the most prominent, recent research proposes using a combination of DRAM and PCM, also called hybrid memory, to best fulfill the memory requirements of future applications. On the software side, developers today increasingly prefer managed languages for improved productivity. Managed workloads are ubiquitous, yet, prior work in making the best use of heterogeneous hardware through scheduling on different core types, performance prediction for frequency scaling, and dynamic memory management for systems with hybrid memory almost entirely assumes native applications written in C and C++. In this talk, I will discuss new opportunities for improving the performance and efficiency of managed language applications running on heterogeneous hardware. I will first introduce a new performance predictor for multithreaded managed applications that enables accurately estimating the execution time of a managed application at a different frequency setting. I will then discuss the challenge of scheduling concurrent garbage collection, a critical component of all managed runtimes, on a heterogeneous multicore. Our proposed scheduler dynamically adjusts the amount of time the collector threads spend on the high performing versus the slow core leading to improved efficiency and better performance compared to existing proposals. Finally, I will briefly share early results and our experiences with building a new garbage collector for systems with hybrid memory that mitigates a major drawback of PCM i.e., limited lifetime of individual cells, while also improving energy efficiency. In all three case studies, I will show how making the language runtime aware of the underlying hardware leads to a higher reduction in energy consumption without sacrificing too much performance.
I am a fourth year Ph.D. student in the Department of Electronics and Information Systems at Ghent University in Belgium. I am pursuing my degree under the supervision of Lieven Eeckhout. Before moving to Ghent in 2012, I spent two years as an Early Stage Researcher at the Foundation of Research and Technology (FORTH) in Heraklion, Greece. My research at FORTH was funded by an EU Marie Curie fellowship. I got my M.S. in Electrical and Computer Engineering at the University of Illinois at Urbana Champaign in 2009. I was a recipient of the J. William Fulbright scholarship from the U.S. Department of State. Before all the foreign travels, I got my B.Sc. in Electrical Engineering in 2006 from the University of Engineering and Technology in Lahore, Pakistan.